(1) FIELD OF THE INVENTION
The invention relates to the general field of semiconductor integrated circuits, more particularly to the formation of the spacers that form part of the LDD salicide process.
(2) DESCRIPTION OF THE PRIOR ART
Field Effect Transistors (FETs), in their simplest form, comprise a body of semiconducting material, usually silicon, having two regions of opposite conductivity type to its own, embedded within it and spaced a short distance apart. Said regions of opposite conductivity type are referred to as source and drain regions, the region between them being referred to as the gate region. In most FET designs the surface of the silicon in the gate region is covered with a thin layer of silicon oxide. Electrically separate electrodes contact all three regions.
Normally, when voltage is applied between source and drain, very little current flows since one of the two PN junctions (relative to the silicon body) will always be back biassed. When, however, voltage of the right polarity is applied to the gate the concentration of minority carriers in a thin layer immediately beneath the gate oxide can be increased to a level sufficient for it to assume the same conductivity type as the source and drain regions, thereby allowing current to flow between them.
FETs operate most efficiently if the area of the interface between source/drain and gate region is kept as small as possible and, additionally, if the resistivity of the source/drain regions at said interface is as high as possible. However, this requirement conflicts with the requirement that any series resistance introduced into the basic FET circuit by the source and drain must be kept as low as possible.
These two conflicting sets of requirements have been largely reconciled in the Lightly Doped Drain (LDD) design, an example of which is illustrated in FIG. 1 as a schematic cross-section. Source and drain regions 13 and 14, respectively, are embedded within silicon body 11, separated from one another by gate region 15. For an NPN FET design, body 11 will be P type while regions 13 and 14 are of type N+, i.e. low resistivity, satisfying the requirement that they introduce minimum series resistance into the circuit. To satisfy the requirement of high resistivity and small area at the interface with region 15, shallow layers 17 of type N--, i.e. high resistivity, extend outward a short distance from regions 13 and 14 to form the source/drain interface with gate region 15.
Since FIG. 1 is not drawn to scale, it does not bring out the fact that the dimensions of the various regions are very small. Furthermore, it is essential that regions 13, 14, and 17 all be very precisely located relative to one another. Also, regions 13 and 14 as well as the top surface of oxide layer 16 must all be fully covered by suitable electrical contacts that do not accidentally connect (short circuit) to one another.
These latter requirements are met by use of the Self Aligned Silicide (Salicide) process. Initially a body of silicon is provided that includes field isolation regions of thick oxide, such as 12 in FIG. 1. The entire body is then coated with a thin layer of oxide (such as 16). Said layer is selectively removed in the region to the left of arrow 1 in FIG. 1.
Using the remaining portions of thin oxide layer 16 as a mask, N+ region 10 is formed, by standard diffusion methods, and serves the purpose of a buried contact that will eventually connect the drain of the device seen in the figure to the gate of a similar device (not shown). This is followed by the deposition of a layer of polycrystalline silicon (poly) such as 18 or 118 in FIG. 1.
The poly layer is then selectively removed in the areas between arrows 1 and 2 and to the right of arrow 3, leaving pedestal 118 above gate region 15. The entire structure is now subjected to an ion implantation process to produce a shallow, lightly doped layer where poly has been removed.
A layer of silicon oxide is then selectively formed on the vertical side walls below arrows 1, 2, and 3, to form spacers 9 and 19, and the structure is subjected to a second ion implantation process, to form the relatively deep, heavily doped, layers 13 and 14. Region 17 is now all that is left of the previously formed lightly doped layer. The structure shown in FIG. 1 has now been achieved.
Because of misalignment problems, it can happen that the edge of the afore-mentioned poly layer to the left of arrow 1 ends up too far to the left, leaving a small area at the surface of buried contact 10 unprotected by oxide during the etch removal of the poly. Consequently, V-shaped trench 5 may unintentionally be etched into the silicon surface, as shown in FIG. 2. Such a trench can cause serious problems such as short circuiting all the way through the buried contact down to the main silicon body 11. The present invention provides a method for achieving the structure of FIG. 1, with no possibility of trench formation.
To complete the process of making full, but non-touching, contacts to the source, drain, and gate regions, spacer 9 is selectively removed, leaving spacers 19 in place. Then, a layer of a refractory metal is deposited over the entire structure which is then subjected to a heat treatment of sufficient intensity to cause said refractory metal layer to react with underlying poly layers 18 and 118 and to be fully converted to a silicide.
Finally, a selective etch treatment is used to remove any unreacted (non-silicided) refractory metal from the structure, in particular those portions of said refractory metal layer that were in contact with spacers 19, as opposed to poly layer 18 or 118. This completes the salicide process.
A number of issued patents describe various apsects of and refinements to the salicide process but none, of which we are aware, addresses the above discussed problem of potential shorting through a buried contact layer. For example, Matsuoka (U.S. Pat. No. 5,053,349 Oct. 1, 1991) teaches several ways to use a refractory metal layer to connect a poly layer to the source, drain, and gate regions. With tungsten this is achieved by means of a deposition technique that causes metal to be selectively deposited on poly but not on oxide (spacers). With titanium a similar result is achieved by forming the silicide and then selectively etching. In Matsuoka's invention, the FET design is not of the LDD type and source/drain regions are formed through diffusion rather than ion implantation.